The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. However, the smaller feature size may lead to more leakage current. As the demand for even smaller electronic devices has grown recently, there has grown a need for reducing leakage current of semiconductor devices.
As semiconductor technologies evolve, fin field effect transistors (FinFETs) have emerged as an effective alternative to further reduce leakage current in semiconductor devices. In a FinFET, an active region including the drain, the channel region and the source protrudes up from the surface of the semiconductor substrate upon which the FinFET is located. The active region of the FinFET, like a fin, is rectangular in shape from a cross section view. In addition, the gate structure of the FinFET wraps the active region around three sides like an upside-down U. As a result, the gate structure's control of the channel has become stronger. The short channel leakage effect of conventional planar transistors has been reduced. As such, when the FinFET is turned off, the gate structure can better control the channel so as to reduce leakage current.
The formation of fins of a FinFET may include recessing a substrate to form recesses, filling the recesses with a dielectric material, performing a chemical mechanical polish process to remove excess portions of the dielectric material above the fins, recessing a top layer of the dielectric material, so that the remaining portions of the dielectric material in the recesses form shallow trench isolation (STI) regions, depositing a gate electrode layer over the fins to form the FinFET.
A chemical mechanical polishing (CMP) process may be used to planarize the top surface of the gate electrode layer. During the CMP process, a wafer comprising the FinFET is placed in a wafer carrier. The wafer carrier is moved downward towards a polishing pad. A chemical solution, referred to as a slurry, is deposited onto the surface of the polishing pad and under the wafer to aid in the planarization process. The wafer carrier is positioned so that the face of the wafer contacts the polishing pad and the slurry. In the CMP process, the surface of the gate electrode layer may be polished using a combination of mechanical and chemical forces.